The present invention relates generally to analog-to-digital converters, and more particularly to an A/D converter comparable in speed to flash A/D converters.
Two approaches are available for analog-to-digital conversion. One is a serial method called successive approximation A/D algorithm which is basically a tree search through all possible quantization levels, where each conversion step selects the next branch to follow based on the result of the previous estimate. While it requires only one comparator, the A/D conversion process is several times slower than the sampling rate. The second approach is the parallel A/D conversion architecture, which is commonly referred to as flash A/D conversion, and provides the high speed approach to quantizing an analog signal. This architecture relies on a technique where all of the possible quantization levels are simultaneously compared to the analog input signal. To compare all the quantization levels of an N-bit A/D structure, 2.sup.N -1 comparators are required. As a result, shortcomings inherent in the conventional flash A/D converter are that a substantial amount of chip size is required for circuit integration and a substantial amount of energy is dissipated.